1. Field of the Invention
The present invention relates to a substrate used in a semiconductor package, a semiconductor package itself, and a method for manufacturing such substrates and semiconductor packages.
2. Description of the Related Art
As semiconductor integrated circuits have become increasingly dens, the number of input/output (I/O) leads has been increasing. This tendency requires semiconductor packages to accommodate a large number of I/O leads of the IC chips. Such packages are mounted on printed wiring board
Two types of semiconductor packages are known, namely, a package with a line of I/O terminals along the periphery, and a package with multiple lines of I/O terminals arranged in full matrix or perimeter array. The former is typically known as QFP (Quad Flat Package). To increase the number of leads in QFP, the lead pitch must be reduced. However, if the pitch is narrowed to 0.5 mm or less, a highly advanced technique is required to connect the leads to the wiring board. The latter is known as an array type package. Array-type packages are suitable to higher I/O integrated circuits because a large number of pins can be arranged at a relatively wide pitch. A conventionally known array type package is PGA (pin grid array). The array-type package is also known as an insertion type package, and is not so suitable to a surface mount package. To overcome this problem, BGA (ball grid array) packages that are suitable for surface mounting have been developed.
On the other hand, as the size of electronic devices become smaller, demand for reducing the package size has increased. To response to this demand, a so-called chip size package (CSP) that is almost equal in size to a semiconductor chip has been proposed. CSP is configured to have connection terminals to the external wiring board, which are included within the surface-mounted area of the semiconductor chip, instead of around the semiconductor chip. CSP is fabricated by, for example, attaching a polyimide film having preformed bumps onto the surface of the semiconductor chip, electrically connecting the chip and the substrate by gold leads, and encapsulation-potting the device by epoxy-resin potting (NIKKEI MATERIAL and TECHNOLOGY 94.4 No. 140, pp.18-19). Another example of fabricating CSP is by forming metallic bumps on a temporary substrate for connection to the semiconductor chip and the external wiring board, face-down bonding the semiconductor chip, and transfer-molding the chip on the temporary substrate (Smallest Flip-Chip-Like package CSP; The Second VLSI Packaging Workshop of Japan, pp.46-50, 1994).
However, the above-described semiconductor package must have through-holes or via holes in order to electrically connect the semiconductor chip to the connection terminals (e.g., solder balls) to the printed wiring board. To be more precise, the semiconductor chip is connected to a conductive pattern formed on the package substrate, and the conductive pattern is connected to the connection terminals provided to the rear face of the substrate via through-holes. Generally, the substrate is drilled to form a through-hole, which is then filled with a metal by plating. Accordingly, the manufacturing process of the package substrate becomes complicated. In addition, friction heat during the drilling process results in high temperatures and adherence of resin smears to the internal copper clad layer, resulting in poor electrical conductivity.
To avoid the complication of manufacturing process and deterioration in electrical conductivity, a board (i.e., a copper-clad laminate) in which through-hole are formed in advance at connecting positions may be used. However, even if using such a holed board, the fineness of the interconnection (or through-holes) is restricted. Further problems exist. For example, conductive patterns (or circuit patterns) are generally formed by selectively etching the copper clad, and the etching precision is determined by the thickness of the copper clad. In order to form a fine conductive pattern on the package substrate, the copper clad used in the laminate board must be thin, or alternatively, the thickness of the copper foil must be reduced at some point during the patterning step. This means that the manufacturing process for a fine-pattern package substrate is still complicated and troublesome.
If using a laminate with a very thin copper clad, the copper pattern is likely to bend before it is covered with an insulating layer, and it is difficult to handle the laminate board during the formation of the conductive pattern. If the thickness of the copper clad is reduced during the pattern forming, the number of steps increases. In addition, the etching precision in terms of depth must be rigorously controlled, and work efficiency may drop. With conventional techniques, it is difficult to fabricate a package substrate with fine conductive patterns and fine interconnections (i.e., through-holes).
This invention was conceived in order to overcome the problems of the prior art, and it is one of the objectives of the invention to provide a substrate for a semiconductor package that has a fine circuit pattern, with high reliability for electrical connection and a simple structure.
It is another objective of the invention to provide a method for manufacturing a substrate for a semiconductor package, which allows a fine pattern to be formed in a reliable manner.
It is still another objective to provide a semiconductor package using the above-mentioned substrate and a manufacturing method thereof.
To achieve these objectives, a substrate for use in a semiconductor package comprises a base having pillar-like interconnections and a resin filling a gap between the interconnections, and a conductive pattern formed on the base. The interconnection is made of a first metal having a first etching characteristic. The conductive pattern is made of a second metal that has a second etching characteristic different to the first etching characteristic with respect to a same etchant.
The first metal is selected from copper (Cu), copper alloy, or iron-nickel alloy. The second metal is selected from nickel (Ni), cromium (Cr), titanium (Ti), tin (Sn), zinc (Zn), or an alloy containing at least one of these elements.
Preferably, the conductive pattern consists of a second metal layer and a third metal layer formed on the second metal layer. In this case, the etching characteristic of the second metal layer is different to that of the first metal with respect to a same etchant.
In the second aspect of the invention, a semiconductor package comprises a substrate including a base with pillar-like interconnections, and a chip mounted on the first surface of the substrate so as to be electrically connected to the interconnections. The interconnections are made of a first metal, and the gap between the interconnections is filled with a resin. A conductive pattern made of a second metal is formed on the base. The second metal has an etching characteristic different from that of the first metal with respect to the same etchant. The semiconductor package also has solder balls connected to the interconnection at a second surface of the substrate opposite to the first surface. The semiconductor chip is encapsulated with a resin seal.
In the third aspect of the invention, a method for fabricating a substrate for use in a semiconductor package is provided. In this method, a composite metal laminate consisting of a first metal layer, second metal layer, and a carrier layer positioned in this order is prepared. The first metal layer has an etching characteristic different from that of the second metal layer with respect to the same etchant. Then, the first metal layer is selectively etched until the second metal layer is exposed, thereby forming pillar-like interconnections. The gap between the interconnections is filled with a resin so as to form a resin base with interconnections. Then, the carrier layer is removed from the second metal layer, and the second metal layer is selectively etched until the first metal layer or the resin base is exposed, thereby forming a conductive pattern on the resin base. The carrier layer is, for example, a polyimide film.
In an alternative method, the carrier layer is a metallic layer. To be more precise, a composite metal laminate consisting of a first metal layer, second metal layer, and a third metal layer positioned in this order is prepared. The first metal layer has an etching characteristic different from that of the second metal layer. The surface of the third metal layer is covered with a resist, and the first metal layer is selectively etched until the second metal layer is exposed, thereby forming a predetermined pattern of interconnections. The gap between the interconnections is filled with a resin so as to form a resin base with interconnections. Then, the third metal layer is selectively etched by a first etchant until the second metal layer is exposed, thereby forming a predetermined pattern. Subsequently, the second metal layer is selectively etched by a second etchant using said pattern as an etching mask until the first metal layer or the resin base is exposed, thereby completing a conductive pattern on the resin base.
During the fabrication of a semiconductor package, an insulating layer is placed over the conductive pattern, leaving a portion of the conductive pattern exposed, and a semiconductor chip is placed onto the exposed conductive pattern. The semiconductor chip is electrically connected to the interconnections. Finally, the entirety of the semiconductor chip is encapsulated with a resin seal.
The methods provided by the present invention do not require drilling the substrate for forming interconnections. In addition, the substrate can maintain sufficient mechanical strength during the patterning of the interconnections because of the carrier layer (either non-metallic or a metallic layer). The resultant substrate has a fine conductive pattern and interconnection, while guaranteeing reliable electric conductivity.